Description
The Secure Flag passed to Versal™ Adaptive SoC’s Trusted Firmware for Cortex®-A processors (TF-A) for Arm’s Power State Coordination Interface (PSCI) commands were incorrectly set to secure instead of using the processor’s actual security state. This would allow the PSCI requests to appear they were from processors in the secure state instead of the non-secure state.
Related CPE's
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CVSS impact metrics
Missing metrics for CVSS V
CVSS V3.1
CVSS V3.0
CVSS V2.0
Information
Source identifier
Vulnerability status
Awaiting analysis
Published
2025-11-23T18:15:55.163
3 weeks agoLast modified
2025-12-19T04:16:01.207
11 hours ago